The present invention relates to a semiconductor technology device, and more particularly, to a delay locked loop circuit of a semiconductor device for performing a delay locking operation with a minimum update cycle although a high speed clock signal is applied.
A synchronous semiconductor memory device such as Double is Data Rate Synchronous DRAM (DDR SDRAM) uses an internal clock to transmit data to external devices. Here, the internal clock is synchronized with an external clock inputted from an external device such as a memory controller CTRL.
Therefore, it is useful to temporally synchronize the external clock from the memory controller with data from a memory in order to stably transmit data between the memory and the memory controller.
The memory outputs data by synchronizing the data with an internal clock. Although the internal clock is synchronized with an external clock when the internal clock is initially applied to the memory, the internal clock may get delayed while passing through constituent elements in the memory and become dissynchronized when the internal clock is outputted to the outside of the memory.
Therefore, in order to stably transmit data outputted from the memory, it is necessary to synchronize the internal clock with the external clock by compensating for a data loading time of loading data to the internal clock for accurately locating the delayed internal clock at an edge or a center of an external clock from the memory controller.
To perform such an operation, a clock synchronization circuit was introduced. The clock synchronization circuit includes a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.
If a frequency of an external clock is different from a frequency of an internal clock, the phase locked loop (PLL) circuit is generally used because it uses a frequency multiplication function to synchronize clocks having different frequencies. However, if a frequency of an external clock is equal to a frequency of an internal clock, the delay locked loop (DLL) is generally used because the delay locked loop (DLL) is not influenced by noise as much as the phase locked loop (PLL) and occupies a smaller area compared to the phase locked loop (PLL).
That is, since a semiconductor memory device uses internal and external clocks having the same frequency, the semiconductor memory device generally includes the delay locked loop (DLL) circuit as a clock synchronization circuit.
FIG. 1 is a block diagram illustrating a delay locked loop circuit according to related art.
Referring to FIG. 1, the delay locked loop (DLL) circuit includes a delay replica model unit 100 for reflecting a delay time of an actual output path to a delay locked clock DLLCLK and outputting the reflected delay locked clock DLLCLK as a feedback clock FBCLK, a phase comparator 120 for comparing a phase of a source clock REFCLK with a phase of the feedback clock FBCLK, and a clock delay unit (140 and 160) for delaying a source clock REFCLK in response to an output signal DECONS of the phase comparator 120 and outputting the delayed source clock REFCLK as a delay locked clock DLLCLK. Also, the delay locked loop circuit further includes a clock buffer unit 180 for buffering a positive clock CLK and a negative clock CLKb and outputting the buffered clock as a source clock REFCLK and a clock driver 190 for driving the delay locked clock DLLCLK as a predetermined driving force.
The clock delay unit includes a delay controller 160 for generating a clock delay control code formed of a plurality of bits in response to a signal DECONS outputted from the phase comparator 120 and a delay 140 for delaying a source clock REFCLK by a delay time decided corresponding to a clock delay control code DECON_CODE<0:N> and outputting the delayed source clock as the delay locked clock DLLCLK.
Although the delay replica model unit 100 was described as reflecting the delay time of the actual output path to the delay locked clock DLLCLK and outputting the reflected clock as the feedback clock FBCLK, the delay time of the actual output path may be decided by modeling the sum of a time taken for transferring the delay locked clock DLLCLK from the delay locked loop circuit to a data output circuit of the semiconductor device and a time for buffering the clock buffering unit 180. Therefore, the delay time of the actual output path defined by the delay replica model unit 100 can be defined in advance when a semiconductor device is designed. After deciding the delay time, the delay time is not changed.
Hereinafter, operation of the delay locked loop DLL circuit according to the related art will be described.
FIGS. 2A and 2B are timing diagrams for describing operation of delay locked loop circuit shown in FIG. 1 and the problem thereof.
Referring to FIGS. 2A and 2B, two timing diagrams of the delay locked loop circuit according to the related art are illustrated for a low frequency source clock REFCLK and a high frequency source clock REFCLK.
Although a reference edge of a source clock REFCLK is not synchronized with that of a feedback clock FBCLK at an initial state of the delay locked loop circuit, the reference edges of the source clock REFCLK and the feedback clock FBCLK are synchronized in FIGS. 2A and 2B. That is, the timing diagram of FIGS. 2A and 2B show states of the clocks after a delay locking operation is complete. Although the reference edge is a rising edge in FIGS. 2A and 2B, the reference edge may be a falling edge.
In more detail, the feedback clock FBCLK is further delayed by at least a delay time D2 of an actual output path with respect to a source clock REFCLK at an initial state of a delay locked loop circuit although it is not shown in FIGS. 2A and 2B. Therefore, the reference edge of the feedback clock FBCLK is behind of the reference edge of the source clock REFCLK.
If the delay locked loop circuit starts a delay locking operation, delay times D1 of the clock delay unit (140 and 160) gradually increase. The delay time D1 is close to ‘0’ at the initial state. Therefore, the delay in feedback clock FBCLK gradually increases. Accordingly, the reference edge of the feedback clock FBCLK is gradually delayed with respect to the reference edge of the source clock REFCLK. However, since the feedback clock FBCLK and the source clock REFCLK have the same frequency, the reference edge of the feedback clock FBCLK and the reference edge of the source clock REFCLK are synchronized at any time point, that is, if the clock delay units 140 and 160 sufficiently delay the feedback clock FBCLK. Although the reference edge of the feedback clock FBCLK is synchronized with a reference edge located one clock tCK behind of the reference of the source clock REFCLK, it is equivalent to a situation where the feedback clock FBCLK and the source clock REFCLK are synchronized without a phase difference because the feedback clock FBCLK and the source clock REFCLK have the same frequency clocks.
If the feedback clock FBCLK and the REFCLK are synchronized through the above described processes, the delay locking operation of the delay locked look circuit ends. Therefore, if the reference edge of the feedback clock is synchronized with the reference edge of the source clock REFCLK as shown, the delay locking operation of the delay locked loop circuit is complete.
In FIGS. 2A and 2B, a reference character D1 denotes a time taken for receiving the source clock REFCLK and outputting the delay locked clock DLLCLK. That is, the reference character D1 represents a time delayed until the source clock REFCLK is outputted as the delay locked clock DLLCLK. Therefore, the time corresponding D1 varies according to the output signal DECONS of the phase comparator 120. In case of a low frequency source clock REFCLK as shown in FIG. 2A, the time D1 is comparatively long. In case of a high frequency source clock REFCLK as shown in FIG. 2B, the time D1 is comparatively short.
A reference character ‘D2’ denotes a time taken for receiving a delay locked clock DLLCLK at the delay replica model unit 100 and outputting the received delay locked clock DLLCKL as the feedback clock FBCLK. That is, the reference character ‘D2’ denotes a time delayed until the delay locked clock DLLCLK is outputted as the feedback clock FBCLK. Therefore, the time D2 is always locked regardless of the operation of the delay locked loop circuit. The time D2 is identical in FIG. 2A for the low frequency source clock REFCLK and FIG. 2B for the high frequency source clock REFCLK.
As shown in FIG. 2A for the low frequency source clock REFCLK, a delay time of the delay replica model unit 110 corresponding to the time D2 is shorter than one cycle tCK of the source clock REFCLK. That is, a time taken for receiving the delay locked clock DLLCLK from the delay replica model unit 100 and outputting it as the feedback clock FBCLK is shorter than one cycle tCK of the source clock REFCLK.
Therefore, the sum of the delay time D1 of the delay replica model unit 100 and the delay times D2 of the clock delay unit (140 and 160) become a time corresponding to one cycle tCK of the source clock REFCLK. Accordingly, the source clock REFCLK and the feedback clock FBCLK having the same frequency have a phase difference as much as one clock cycle tCK.
On the contrary, as shown in FIG. 2B for the high frequency source clock REFCLK, the delay time D2 of the delay replica model unit 100 is longer than one cycle tCK of the source clock REFCK because the frequency of the source clock REFCLK is high frequency. That is, a time taken by the delay replica model unit 100 for receiving the delay locked clock DLLCLK and outputting it as the feedback clock FBCLK is longer than one cycle tCK of the source clock REFCLK.
Therefore, the sum of the delay time D1 of the delay replica model unit 100 and the delay times D2 of the clock delay unit (140 and 160) become longer than a time corresponding to one cycle tCK of the source clock REFCLK. Accordingly, the source clock REFCLK and the feedback clock FBCLK having the same frequency may have a phase difference of two cycles 2×tCK of the source clock REFCLK.
However, if a time taken by a delay locked loop circuit to update one time becomes longer than one cycle tCK of the source clock REFCLK because the delay time of the delay replica model unit 100 becomes longer than one cycle tCK of the source clock REFCLK as shown in FIG. 2B for the high frequency of the source clock REFCLK, it may cause a problem that the phase comparator 120 compares a phase with a feedback clock RBCLK which is not completely updated. Therefore, the delay amounts of the clock delay unit (140 and 160) are greatly changed because the completely updated feedback clock FBCLK is not inputted to the phase comparator 120 although the feedback clock FBCLK is completely updated.
Therefore, it is necessary to perform an additional operation for reducing the delay amounts of the clock delay unit (140 and 160) to synchronize a phase of the feedback clock FBCLK with a phase of the source clock REFCLK. As a result, the delay locked loop circuit takes a longer time to operate.
Since such a problem makes the reference edge of the feedback clock RBCLK to fall behind or lead ahead of the reference edge of the source clock REFCLK, jitters of internal clocks increase.
Since a time taken by a delay locked loop circuit to update is always longer than one cycle tCK of the source clock REFCLK, the time of toggling the source clock until the delay locking operation ends significantly increases. It is because the update of the delay locked loop circuit repeats several times through the delay locking operation.
The delay locking operation of the delay locked loop circuit according to an exemplary embodiment ends before the source clock REFCLK is toggled several times. Therefore, it may be difficult to complete the delay locking operation within a desired value because the toggling time of the source clock REFCLK increases until the delay locking operation completely ends.
The above mentioned problems may occur more frequently if the delay locked loop circuit receives high frequency external clocks CLK and CLKB. Lately, a semiconductor device is generally designed to use high frequency external clocks CLK and CLKB. Therefore, the above mentioned problems may occur frequently in semiconductor devices.